An important circuit element of most electronic circuits is the transistor. There are numerous transistor families, such as bipolar junction transistors and field effect transistors. One important transistor family is the metal-oxide-semiconductor field effect transistors (MOSFET). There are MOSFETs for use in small signal applications and other designed for power applications. A common power MOSFET is the vertical or trench MOSFET. Referring to FIG. 1, a basic trench MOSFET according to the conventional art is shown. The topology of the illustrated trench MOSFET 100 is commonly referred to as a griped cell MOSFET. The striped trench MOSFET 100 comprises a source contact (not shown), a plurality of source regions 110, a plurality of gate regions 115, a plurality of gate insulator regions 120, a plurality of body regions 125, a drift region 130, a drain region 135, and drain contact (not shown).
The body regions 125 are disposed above the drift region 130 opposite the drain region 135. The source regions 110, gate regions 115 and the gate insulator regions 120 are disposed within the body regions 125. The gate regions 115 and the gate insulator regions 120 are formed as substantially parallel-elongated structures. Each gate insulator region 120 surrounds a corresponding gate region 115, electrically isolating the gate region 115 from the surrounding regions 110, 125, 130. The gate regions 115 are coupled to form a common gate of the device 100. The source regions 110 are formed as substantially parallel-elongated structures along the periphery of the gate insulator regions 120. The source regions 110 are coupled together to form a common source of the device 100, by the source contact. The source contact also couples the source regions 110 to the body regions 125.
The source regions 110 and the drain region 135 are heavily n-doped (N+) semiconductor, such as silicon doped with phosphorous or arsenic. The drift region 130 is lightly n-doped (N−) semiconductor, such as silicon doped with phosphorous or arsenic. The body regions 125 are p-doped (P) semiconductor, such as silicon doped with boron. The gate regions 115 are heavily n-doped (N+) semiconductor, such as polysilicon doped with phosphorous. The gate insulator regions 120 may be a dielectric, such as silicon dioxide.
When the potential of the gate regions 115, with respect to the source regions 110, is increased above the threshold voltage of the device 100, a conducting channel is induced in the body region 125 along the periphery of the gate insulator regions 120. The striped trench MOSFET 100 will then conduct current between the drain region 135 and the source regions 110. Accordingly, the device 100 is in its on state.
When the potential of the gate regions 125 is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region 135 and the source regions 110 will not cause current to flow there between. Accordingly, the device 100 is in its off state and the junction formed by the body region 125 and the drain region 135 supports the voltage applied across the source and drain.
The channel width of the striped trench MOSFET 100 is a function of the width of the plurality of the source regions 110. Thus, the striped trench MOSFET 100 provides a large channel width to length ratio. Therefore, the striped trench MOSFET may advantageously be utilized for power MOSFET applications, such as switching elements in a pulse width modulation (PWM) voltage regulator.
In the conventional art, there are numerous variations of the MOSFET made to improve the performance of the device. For example, the trench MOSFET may be modified to include a super-junction, a source shield with thick oxide, a reduce conductor path to the drain in combination with a thick gate-to-drain oxide, and the like.
A super-junction MOSFET can achieve an On-state resistance value below the limit of silicon for a given semi-infinite planar junction breakdown voltage. The presence of the alternative p-n regions allows the increase of drift region doping, depending on p-n region widths. The drift region doping can be increased by reducing the p and n region widths to maintain low lateral electric fields needed to maintain breakdown voltages. However, the lateral p-n junction regions limit the achievable conductive drift region widths due to the existence of built in depletion regions. This makes super-junction based MOSFET devices less advantageous for low voltage power MOSFETs (e.g., 30V or less) where epitaxial doping increments needed to see a decrease in total On-state resistance primarily composed of channel resistance is more. For high voltage power MOSFETs (e.g., 150V or more), multiple epitaxial or trench refill techniques are used to fabricate alternate p-n regions makes achieving narrow n-region widths for deeper p-n unction regions challenging and expensive.
At relatively low voltages (e.g., 150V or less), to overcome the problems associated with using vertical p-n junction resurface regions and be able to reduce On-state resistance below silicon limits, lateral depletion of additional n-doping is achieved using gate or source connected shielding structures surrounding the n-epitaxial region are employed. However, devices based on such shield techniques need thicker oxide layer (e.g., 0.5 um or more) between the gate or source shield structures and silicon to achieve higher breakdown voltages e.g., 150V or more). The technologically challenging thicker oxides in a trench, needed to achieve high breakdown voltages, is a significant barrier in utilizing such shield techniques. Furthermore, shield techniques showing low On-state resistance inevitably increase the device capacitance and hence charge needed to switch the transistor on and off resulting in increase switching loss. Similar drawbacks are experienced, by gate-to-drain thick oxide techniques. As a result, shield technique MOSFETs are limited to relatively low switching frequencies (e.g., 1 MHz or less). Accordingly, it is desirable to have a device structure that is an improvement over super-junction, shield structure, and gate-to-drain thick oxide transistors that achieve low on-state resistance with minimal increase in device capacitance and relatively high breakdown voltages even when using thinner oxide layers between structures.